1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of a dielectric interlayer between and over circuit elements including closely spaced lines, such as gate electrodes, polysilicon interconnect lines and the like.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and cost effectiveness. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline silicon layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors, resistors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the “wiring,” i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of polysilicon lines and the like within the device layer so that one or more additional “wiring” layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in very advanced devices, low-k materials having a permittivity of 3.5 or less are used. The metal lines and the surrounding dielectric material will be referred to hereinafter as a metallization layer. Between two adjacent metallization layers and also between the device layer and the first metallization layer, respective dielectric interlayers are formed through which metal-filled openings are formed to establish the electrical connection between metal lines or between circuit elements and metal lines. In typical applications, the dielectric interlayer separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates. Upon further device scaling, resulting in gate lengths of MOS transistors on the order of 50 nm or even less, the distances between neighboring circuit elements, such as polysilicon lines, gate electrodes and the like are also reduced and have now reached 200 nm and less in modern CPUs. It turns out, however, that the gap-fill capabilities of well-established high rate PECVD techniques for the deposition of silicon dioxide may no longer suffice to reliably form a dielectric interlayer, as will be described in more detail with reference to FIGS. 1a-1c. 
In FIG. 1a, a semiconductor device 100 comprises a substrate 101 that may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate having formed thereon a device layer 102 including, for instance, a silicon layer 110 having formed thereon a structure 103 that may comprise closely spaced lines 104. Hence, the device layer 102 may represent a substantially crystalline silicon region in which and on which circuit elements, such as field effect transistors, capacitors and the like, are formed. The structure 103 may represent an area having a plurality of dense polysilicon lines, or the lines 104 may represent portions of gate electrodes of transistor elements. The lines 104 may have formed on sidewalls thereof corresponding spacer elements 105, as are typically used for forming gate electrode structures. An etch stop layer 109, typically comprised of silicon nitride, is formed over the device layer 102 to cover the layer 110 and the line structure 103. A silicon dioxide layer 107 is formed above the etch stop layer 109 to completely enclose the line structure 103.
A typical conventional process flow for forming the device 100 as shown in FIG. 1a may include the following processes. After fabrication processes to form circuit elements, such as transistors, capacitors and the line structure 104, which include lithography, deposition, etch, implantation and other techniques, the etch stop layer 109 is formed, typically by plasma enhanced chemical vapor deposition (PECVD), since PECVD of silicon nitride may be accomplished at moderately low temperatures of less than approximately 600° C., which is compatible with preceding manufacturing processes and materials, such as metal silicides and the like. As previously discussed, the ongoing shrinkage of feature sizes also entails that a distance between neighboring circuit elements, such as a distance 111 between the closely spaces lines 104, is reduced and may be less than approximately 200 nm in currently manufactured CPUs of the 90 nm technology node. Hence, any deposition techniques for forming a dielectric layer for embedding the line structure 103 with open spaces therebetween have to meet the requirements of an appropriate fill capability to reliably and completely fill the empty spaces between the densely spaced lines 104. By means of well-established PECVD process recipes for silicon nitride, the layer 109 may be deposited in a more or less conformal fashion with a thickness in the range of approximately 10-80 nm. Thereafter, the silicon dioxide layer 107 is deposited, which is typically done by PECVD on the basis of precursors TEOS (tetra-ethyl-ortho-silicate) and oxygen, since PECVD, contrary to thermal TEOS CVD, allows the deposition of silicon dioxide in a moderately conformal manner, yet with significantly less gap filling qualities compared to thermal CVD, with relatively high mechanical stability at temperatures below 600° C. at high deposition rates, which provides a high production yield. Moreover, PECVD cluster tools are readily available so that the deposition of the silicon nitride layer 109 and the PECVD silicon dioxide layer 107 may be performed in a highly efficient manner.
However, when the distance 111 approaches approximately 200 nm, it turns out that the fill capabilities of well-established PECVD techniques for depositing silicon dioxide on the basis of TEOS and oxygen may not be adequate to completely fill the empty spaces between the lines 104, thereby creating voids 106, which may lead to reliability concerns during the further processing of the semiconductor device 100. Moreover, it should be noted that the silicon dioxide layer 107 has a certain topography caused by the underlying structure of the device layer 102, for instance, by the line structure 103, which may jeopardize subsequent manufacturing processes, such as a photolithography step for forming contact openings to underlying portions of circuit elements located in the layer 110 or on the lines 104. Consequently, standard process flow requires that the silicon dioxide layer 107 be planarized, typically by chemical mechanical polishing (CMP), wherein excess material of the silicon dioxide layer 107 is removed by chemical and mechanical interaction with a slurry and a polishing pad to finally obtain a substantially planarized surface of the silicon dioxide layer 107. The CMP process itself is a highly complex process and requires sophisticated process recipes, which significantly depend on the characteristics of the silicon dioxide layer 107, such as density, mechanical stress, water contents and the like. Hence, a great deal of effort has been made to develop corresponding process recipes for reliable and reproducible CMP processes for PECVD TEOS silicon dioxide, as this material is frequently used for a dielectric interlayer in silicon-based semiconductor devices and even in devices formed from other semiconductors.
FIG. 1b schematically shows the semiconductor device 100 after the planarization of the silicon dioxide layer 107 by well-established CMP recipes to form a substantially planarized silicon dioxide layer 107a. Moreover, an anti-reflective coating (ARC) layer 108 is formed on the silicon dioxide layer 107a, wherein the characteristics of the ARC layer 108 are designed for a subsequent photolithography process for patterning a resist layer to etch respective contact openings to the device layer 102. The ARC layer 108 may be comprised of silicon oxynitride, wherein typically the oxygen/nitrogen ratio is correspondingly adapted to obtain a specified index of refraction and extinction coefficient in order to achieve, in combination with a specified layer thickness, a minimum back reflection of the exposure radiation used in the subsequent photolithography. Typically, the ARC layer 108 is formed by PECVD, wherein the oxygen/nitrogen ratio may be adjusted by controlling the supply of corresponding precursor gases.
During the CMP process for forming the planarized layer 107a and the subsequent photolithography followed by anisotropic etch techniques, the voids 106 created during the deposition of the silicon dioxide layer 107 may result in significant process variations and increased defect rates, especially during the anisotropic etch processes, so that the above-described well-established process flow may no longer be adequate for devices having distances between neighboring lines of approximately 200 nm or less, which are typically encountered in semiconductor products of the 90 nm technology node.
FIG. 1c schematically shows the semiconductor device 100 according to a further conventional approach. The semiconductor device 100 of FIG. 1c substantially corresponds to the device 100 shown in FIG. 1a, with the exception that the dielectric layer formed on the silicon nitride layer 109 is deposited by a different deposition technique having a significantly enhanced gap filling capability to avoid the creation of the voids 106 (FIG. 1a). Hence, in FIG. 1c, a silicon dioxide layer 117 is provided that may be formed by a thermal CVD process on the basis of TEOS and ozone, which generates a silicon dioxide film exhibiting excellent gap filling capabilities, that is, this deposition technique provides excellent conformality, and may even display a “flow-like” behavior, thereby allowing reliable filling of the empty spaces between the lines 104. In view of the film characteristics, the thermal CVD process is typically performed at significantly higher pressures compared to the plasma enhanced deposition technique, for example in the range of 200-760 Torrs, and is therefore denoted as “sub-atmospheric CVD” (SACVD). Another deposition technique for silicon dioxide is the plasma enhanced deposition in which a high-density plasma is used, thereby also achieving excellent conformality and gap-filling capabilities. After the formation of the silicon dioxide layer 117 in accordance with one of these two deposition techniques, further processing may be continued as is described with reference to FIG. 1b. That is, the silicon dioxide layer 117 is planarized by CMP and subsequently an ARC layer may be deposited for the subsequent photolithography. Despite the superior gap filling capabilities of the SACVD and the high density plasma (HDP) CVD, it turns out that the very different film characteristics of the silicon dioxide layer 117 compared to the plasma enhanced CVD film 107 require completely new CMP and substrate handling strategies and may also bring about a significant reduction in production yield due to reduced deposition rates, particularly when the SACVD technique is employed.
For example, the silicon dioxide layer 117 is less dense than the layer 107 and also readily absorbs water, which leads to an alteration of the intrinsic stress in the layer 117. Typically, the SACVD TEOS silicon dioxide exhibits a moderate tensile stress immediately after deposition, which may decrease and turn into compressive stress with the increasing absorption of water from the ambient atmosphere. Upon removal of the absorbed water, for example, by heating the substrate, again tensile stress is created in excess of the initially tensile stress, which is finally again achieved upon cooling the substrate. Thus, upon contact with air or water, the SACVD TEOS silicon dioxide layer 117 undergoes a stress hysteresis, which may be inadequate for sophisticated semiconductor devices, as stress and strain engineering becomes more and more important for extremely scaled devices. Due to the different mechanical characteristics of the layer 117 and the fact that intense contact with water during the CMP process may occur, great efforts have to be made to establish new CMP recipes. In combination with a reduced deposition rate, compared to the plasma enhanced CVD TEOS silicon dioxide, the process for forming the dielectric interlayer, that is a layer stack comprising the silicon nitride layer 109, the silicon dioxide layer 117 and the ARC layer 108 is cost-intensive and may bring about further issues related to the different film characteristics of the silicon dioxide layer 117 with respect to CMP, substrate handling, strain engineering and the like.
In view of the problems identified above, there exists a need for a cost-efficient technique for forming a dielectric interlayer for the first metallization layer, especially for devices having empty spaces between densely formed lines with approximately 200 nm or less.